Random testing of multi-port static random access memories

Author

Karimi, F. ; Meyer, F.J. ; Lombardi, F.

Author_Institution

LTX Corp., San Jose, CA, USA

fYear

2002

fDate

2002

Firstpage

101

Lastpage

106

Abstract

This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams. In the state diagrams, transition probabilities are established by considering the effects of the memory operations (read and write), the lines involved in the fault (bit and word-lines) as well as the types and number of ports. Test lengths per cell at 99.9% coverage are given.

Keywords

Markov processes; SRAM chips; fault diagnosis; integrated circuit testing; multiport networks; probability; production testing; Markov state diagrams; coverage; inter-port faults; memory operations; multi-port static random access memories; random testing; test lengths; transition probabilities; word-lines; Application software; Electrical fault detection; Embedded computing; Fault detection; Hardware; Logic testing; Manufacturing; Memory architecture; Production; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on

ISSN

1087-4852

Print_ISBN

0-7695-1617-3

Type

conf

DOI

10.1109/MTDT.2002.1029770

Filename

1029770