DocumentCode
2194553
Title
A novel memory array based on an annular single-poly EPROM cell for use in standard CMOS technology
Author
Dray, C. ; Gendrier, P.
Author_Institution
Central R&D, STMicroelectronics, Crolles, France
fYear
2002
fDate
2002
Firstpage
143
Lastpage
148
Abstract
Within the scope of non-volatile memories, CMOS compatibility and portability are serious issues. We describe here an edgeless single-poly floating gate p-channel memory cell, which can be embedded into a novel memory array architecture. It features high electrical performance together with a robustness with respect to the process. It has been processed in a 0.18 μm HCMOS technology from STMicroelectronics, Crolles.
Keywords
CMOS memory circuits; EPROM; cellular arrays; 0.18 micron; CMOS compatibility; HCMOS technology; STMicroelectronics; annular single-poly EPROM cell; electrical performance; memory array; nonvolatile memories; portability; robustness; single-poly floating gate p-channel cell; CMOS technology; Costs; EPROM; Isolation technology; Leakage current; Memory architecture; Nonvolatile memory; Packaging; Research and development; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on
ISSN
1087-4852
Print_ISBN
0-7695-1617-3
Type
conf
DOI
10.1109/MTDT.2002.1029775
Filename
1029775
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