Title :
Validated 90nm CMOS technology platform with low-k copper interconnects for advanced system-on-chip (SoC)
Author :
Devoivre, T. ; Lunenborg, M. ; Julien, C. ; Carrere, J.-P. ; Ferreira, P. ; Toren, W.J. ; VandeGoor, A. ; Gayet, P. ; Berger, T. ; Hinsinger, O. ; Vannier, P. ; Trouiller, Y. ; Rody, Y. ; Goirand, P.-J. ; Palla, R. ; Thomas, I. ; Guyader, F. ; Roy, D. ; B
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16Å EOT-70nm transistors (standard process) or 21Å-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1 Mbit SRAM instances, based on a highly manufacturable 6T 1.36μm2 memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.
Keywords :
CMOS integrated circuits; application specific integrated circuits; cellular arrays; integrated circuit interconnections; lithography; low-power electronics; random-access storage; 16 angstrom; 2.5 V; 21 angstrom; 3.3 V; 70 nm; 90 nm; CMOS; SRAM; SiOC; advanced lithographic tools; advanced system-on-chip; electrical results; low power process; low-k copper interconnects; manufacturable memory cell; morphological features; CMOS process; CMOS technology; Copper; Energy management; Integrated circuit interconnections; Power supplies; Random access memory; System performance; System-on-a-chip; Technology management;
Conference_Titel :
Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on
Print_ISBN :
0-7695-1617-3
DOI :
10.1109/MTDT.2002.1029778
