Converting an embedded low-power SRAM from bulk to PD-SOI

Author

Casu, Mario R. ; Flatresse, Philippe

Author_Institution

Politecnico di Torino, Italy

fYear

2002

fDate

2002

Firstpage

163

Lastpage

167

Abstract

The migration of an embedded 1 Mbit SRAM for low power applications from a 0.13μm bulk to a partially depleted silicon-on-insulator (PDSOI) technology is described in this paper. Floating body effects such as threshold voltage variation and parasitic bipolar turn on and their impact on sense amplifiers, pass-gates based multiplexers and dynamic decoders are addressed. Solutions like the use of body contacts in specific parts are discussed. A SRAM chip with various testable configurations has been taped out.

Keywords

MOS memory circuits; SRAM chips; low-power electronics; multiplexing equipment; silicon-on-insulator; 0.13 micron; PD-SOI; Si; body contacts; dynamic decoders; embedded low-power SRAM; floating body effects; low power applications; parasitic bipolar turn on; partially depleted silicon-on-insulator; pass-gates based multiplexers; sense amplifiers; testable configurations; threshold voltage variation; Capacitance; Circuits; Costs; Differential amplifiers; Microelectronics; Random access memory; Silicon on insulator technology; Testing; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on

ISSN

1087-4852

Print_ISBN

0-7695-1617-3

Type

conf

DOI

10.1109/MTDT.2002.1029780

Filename

1029780