DocumentCode :
2194950
Title :
Functional verification of network processor
Author :
Ma, Pei-Jun ; Jiang, Yong ; Li, Kang ; Shi, Jiang-Yi
Author_Institution :
Dept. Microelectron., Xidian Univ., Xi´´an, China
fYear :
2011
fDate :
9-11 Sept. 2011
Firstpage :
1472
Lastpage :
1475
Abstract :
Network processor is a type of specific instruction set processor which is used to process the data packet and possess specific circuit. In this paper, based on the testbench of network processor, functional coverage models are built by the two types of functional coverage expression provided by SystemVerilog. The functional coverage can be obtained automatically by these models. According to the functional coverage, we can modify the testcases to get a fast convergence of functional coverage, so that the network processor acquires efficient functional verification. To reduce the time to fix bugs´ position, the assertion of property is also discussed in the paper.
Keywords :
hardware description languages; instruction sets; system-on-chip; SystemVerilog; data packet process; functional coverage model; instruction set processor; multicore SoC; network processor functional verification; Computer bugs; Generators; IP networks; Integrated circuit modeling; Monitoring; Protocols; System-on-a-chip; covergroup; functional coverage; network processor; property; testbench;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Ningbo
Print_ISBN :
978-1-4577-0320-1
Type :
conf
DOI :
10.1109/ICECC.2011.6067696
Filename :
6067696
Link To Document :
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