Wire length and width bound generation for high-speed MCM and PCB designs

In this paper a methodology for computation of bounds on MCM and PCB net length and width consistent with timing and noise constraints is proposed. In this method. The initial length and width of each net are used for the AWE-based simulation. For the simulated length and width of the line, the delay and overshoot at receivers are expanded in the form of multi-variable Taylor series of length/width of segments for a multi-pin net. When the resulting linear delay and overshoot functions are bounded by timing and overshoot constraints, the line length and width that satisfy the constraints are obtained by solving a linear programming problem. Computed bounds can be used in practical design to reduce the number of timing and signal integrity violations and shorten the design cycle