Title :
Test of CMOS circuits based on its energy consumption
Author :
Ortega, M.A. ; Rius, J. ; Figueras, J.
Author_Institution :
Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
A modified Keating-Meyer technique to test CMOS circuits by measuring its energy consumption is presented. The circuit is fed by a capacitor being successively recharged while it is excited by a set of test vectors. A Binary Counter is incremented after a quantum of energy has been supplied to the CUT while the circuit is excited by test vectors. The energy cronogram for a given vector set is defined as its Energy Signature. Preliminary experiments show how this energy signature could be used to discriminate non-defective from defective circuits. If the test is applied at a sufficiently low rate the information obtained is equivalent to I/sub DDQ/ testing. Experimental data agree with predicted results and show how bridging and open faults are detected with this method.
Keywords :
CMOS integrated circuits; integrated circuit testing; CMOS circuit; IDDQ testing; Keating-Meyer technique; binary counter; bridging faults; capacitor; energy consumption; energy cronogram; energy signature; open faults; test; CMOS logic circuits; Circuit testing; Counting circuits; Electrical fault detection; Energy consumption; Energy measurement; Fault detection; Logic testing; Switches; Switching circuits;
Conference_Titel :
IDDQ Testing, 1996., IEEE International Workshop on
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-8186-7655-8
DOI :
10.1109/IDDQ.1996.557809
