Performance evaluation of DIP policy on SMT processor system

Author

Zhang, Chaozhong ; He, Liqiang

Author_Institution

Coll. of Comput. Sci., Inner Mongolia Univ., Huhhot, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

4427

Lastpage

4430

Abstract

Simultaneous Multithreading (SMT) processor got its high performance through fetching and executing multiple instructions from concurrent running threads with a shared hardware resources. Dynamic Insertion Policy (DIP) has been shown to have good performance for the cache. In this paper, we port the DIP replacement policy onto SMT processor based computer system, and evaluate the performance of it. The simulation experiments show that although some programs can obtain better performances with DIP policy in SMT processor the overall performance of the combined workloads are not so good as in a CMP processor based computer system.

Keywords

multi-threading; multiprocessing systems; performance evaluation; CMP processor based computer system; DIP replacement policy; SMT processor system; concurrent running thread; dynamic insertion policy; performance evaluation; shared hardware resource; simultaneous multithreading processor; Art; Computational modeling; Computer science; Computers; Educational institutions; Electronics packaging; Multithreading; DIP policy; SMT processor; last level cache; performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Ningbo

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6067715

Filename

6067715