DocumentCode :
2195962
Title :
Gigahertz FPGAs with new power saving techniques and decoding logic
Author :
Channakeshav ; Zhou, K. ; Kraft, R. ; McDonald, J.F.
Author_Institution :
Rensselaer Polytech. Inst., Troy, NY, USA
fYear :
2002
fDate :
2002
Firstpage :
60
Lastpage :
62
Abstract :
The availability of SiGe HBT devices has opened the door for Gigahertz FPGAs. Speeds over 5 GHz have been reported However, to make the idea practical, serious power management and new architectural features have to be included, so that they can be scaled up significantly. This paper elaborates new ideas in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to cut down the number of current trees in the circuit. Selective tree shutdown has been used to reduce power consumption. A new decoding logic has been developed where the address and data lines are shared These ideas have improved the performance of SiGe FPGAs. The operating frequency of the new Configurable. Logic Block (CLB) is 6.8 GHz.
Keywords :
BiCMOS logic circuits; field programmable gate arrays; heterojunction bipolar transistors; logic design; BiCMOS gigahertz FPGAs; SiGe HBT devices; architectural features; configurable logic block; decoding logic; power management; power saving techniques; BiCMOS integrated circuits; Decoding; Energy consumption; Energy management; Field programmable gate arrays; Frequency; Germanium silicon alloys; Heterojunction bipolar transistors; Logic devices; Silicon germanium;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Evolvable Hardware, 2002. Proceedings. NASA/DoD Conference on
Print_ISBN :
0-7695-1718-8
Type :
conf
DOI :
10.1109/EH.2002.1029866
Filename :
1029866
Link To Document :
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