Title :
1.2 Gb/s SONET/SDH demux in CMOS technology
Author :
Romão, Fabio L. ; Soares, João Navarro ; Silveira, Reinaldo ; Van Noije, Wilhelmus A M
Author_Institution :
Lab. de Sistemas Integraveis, Sao Paulo Univ., Brazil
Abstract :
This paper describes the design of a demux to meet the requirements of the SONET STS-24 (synchronous transport signal level 24) at a rate of 1.2 Gb/s, using a standard 0.8 μm DLM CMOS process. True single phase clocked flip-flops sensitive on both clock edges and deep pipeline techniques are used in order to achieve such a clock rate. The circuit also performs the byte alignment specified in the SONET STS-N frame structure definition
Keywords :
CMOS digital integrated circuits; SONET; demultiplexing equipment; synchronous digital hierarchy; telecommunication standards; 0.8 micron; 1.2 Gbit/s; CMOS technology; DLM CMOS process; SONET STS-24; SONET STS-N frame structure definition; SONET/SDH demultiplexer; byte alignment; clock edges; clock rate; deep pipeline techniques; single phase clocked flip-flops; synchronous transport signal level 24; CMOS process; CMOS technology; Circuits; Clocks; Flip-flops; Pipelines; SONET; Signal design; Signal processing; Synchronous digital hierarchy;
Conference_Titel :
Microwave and Optoelectronics Conference, 1995. Proceedings., 1995 SBMO/IEEE MTT-S International
Conference_Location :
Rio de Janeiro
Print_ISBN :
0-7803-2674-1
DOI :
10.1109/SBMOMO.1995.509597
