• DocumentCode
    2195991
  • Title

    A new timing-driven multilayer MCM/IC routing algorithm

  • Author

    Wang, Dongsheng ; Kuh, Ernest S.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1997
  • fDate
    4-5 Feb 1997
  • Firstpage
    89
  • Lastpage
    94
  • Abstract
    In high-performance multilayer routing, time delay is an important performance issue which has not been appropriately addressed by previous multilayer routing approaches. This paper proposes a new timing-driven MCM/IC multilayer routing algorithm, named MLR, considering the Elmore delay as well as some other fundamental performance issues, such as the number of layers, vias and the total wirelength. Algorithm MLR assigns all the nets into the routing layers layer-pair by layer-pair based on the layer assignment algorithm. During each pair-layer routing, the timing-driven Steiner area routing algorithm SOAR is used to generate a Steiner tree for each net while minimizing the Elmore delay of the net. For two nodes to be connected for the net being routed, an optimal path from one node to the other is created by the (α,β)* algorithm. Additionally, when power and ground nets are considered, some signal nets are routed in the limited routing space on the power and ground layer-pair, which is very useful in decreasing the number of layers needed to complete the routing. The proposed algorithm has been implemented and tested on CBL/NCSU and MCC benchmarks and the experimental results are very promising
  • Keywords
    circuit layout CAD; circuit optimisation; delays; integrated circuit layout; multichip modules; network routing; timing; CBL/NCSU benchmarks; Elmore delay; IC routing; MCC benchmarks; MCM routing; MLR; SOAR; layer assignment algorithm; optimal path; pair-layer routing; routing space; signal nets; time delay; timing-driven Steiner area; timing-driven multilayer routing; total wirelength; Algorithm design and analysis; Benchmark testing; Delay effects; Fabrication; High performance computing; Nonhomogeneous media; Performance evaluation; Routing; Steiner trees; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multi-Chip Module Conference, 1997. MCMC '97., 1997 IEEE
  • Conference_Location
    Santa Cruz, CA
  • Print_ISBN
    0-8186-7789-9
  • Type

    conf

  • DOI
    10.1109/MCMC.1997.569350
  • Filename
    569350