10 Gbit/s byte-interleaver and de-interleaver with silicon ICs

Author

Hanke, Gerhardl

Author_Institution

Deutsche Telekom, Darmstadt, Germany

Volume

1

fYear

1995

fDate

24-27 Jul 1995

Firstpage

189

Abstract

For an experimental STM-64 system two very fast silicon MSI circuits were developed and fabricated, which make it possible to multiplex and demultiplex in a byte-by-byte mode up to 10 Gbit/s. To obtain a 4:1 multiplexing (resp. a 1:4 demultiplexing) three identical multiplexer- (resp. demultiplexer-) chips are necessary. Due to economical reasons three of the four channels are filled in the described system with pseudorandom signals

Keywords

SONET; bipolar digital integrated circuits; demultiplexing equipment; elemental semiconductors; interleaved codes; multiplexing; multiplexing equipment; pseudonoise codes; silicon; synchronous digital hierarchy; 10 Gbit/s; SDH; SONET; STM-64 system; Si; bipolar process; byte deinterleaver; byte interleaver; demultiplexer chips; multiplexer chips; pseudorandom signals; silicon IC; silicon MSI circuits; Bit rate; Circuit simulation; Clocks; Demultiplexing; Flexible printed circuits; High speed optical techniques; Optical signal processing; Signal processing; Silicon; Synchronous digital hierarchy;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Optoelectronics Conference, 1995. Proceedings., 1995 SBMO/IEEE MTT-S International

Conference_Location

Rio de Janeiro

Print_ISBN

0-7803-2674-1

Type

conf

DOI

10.1109/SBMOMO.1995.509619

Filename

509619