DocumentCode
2196948
Title
Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced Technology
Author
Chien, Kary
Author_Institution
Semicond. Manuf. Int. Corp., Shanghai
fYear
2007
fDate
8-11 Oct. 2007
Firstpage
9
Lastpage
9
Abstract
Summary form only given. To facilitate the business fast-growing and meet reliability test requirements of advanced technology development and multiple types of products, it is necessary to establish a flexible, fast-responsible, and efficient full-scale reliability testing capability. The reliability testing capability should cover all segments including technology development and qualification, process monitor and reliability assessment of process issues. Innovative test structure like matrix gate oxide structure was designed to improve wafer level reliability (WLR) test efficiency and probe contact resistance (PCR) calibration tool was developed to enhance test accuracy. The side braze assembly (SBA) line was established and significantly reduced the sample preparation cycle time. Moreover, it provides the flexibility to support complicated ESD/ function & design verifications, and product reliability studies using our innovative high-pin-count package solutions. Anti-ESD solution kits were developed to prevent ESD damage during sample preparation & package reliability testing in advanced technology node. Advanced test during burn in (TDBI) system was established to extend the test capability from memory device to mix-signal device. In-house Chip probing (CP) system deepens our understanding on correlation among CP, final test (FT) and reliability performance. Build-in reliability diagnosis system (BIRDS) was formed to manage the reliability data and ensures data integrity. It also creates an opportunity for reliability data systematical statistic analysis.
Keywords
contact resistance; semiconductor device reliability; statistical analysis; data integrity; data systematical statistic analysis; final test; foundry full-scale reliability testing capability setup; high-pin-count package solutions; in-house chip probing system; matrix gate oxide structure; mix-signal device; probe contact resistance calibration tool; process monitor-reliability assessment; product reliability; side braze assembly; test during burn in; wafer level reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2007. ATS '07. 16th
Conference_Location
Beijing
ISSN
1081-7735
Print_ISBN
978-0-7695-2890-8
Type
conf
DOI
10.1109/ATS.2007.109
Filename
4387975
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