Title :
The Region-Exhaustive Fault Model
Author :
Jas, Abhijit ; Natarajan, Suriyaprakash ; Patil, Srinivas
Author_Institution :
Intel Corp., Santa Clara
Abstract :
Device failure mechanisms of today´s deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a collection of gates) with the hypothesis that exercising a region with an exhaustive pattern set can yield coverage on a larger proportion of unmodeled defects. To test out this hypothesis, we use the logic proximity bridge (LPB) fault model as a surrogate for unmodeled defects and grade the region and gate exhaustive patterns against the LPB fault model to gauge their efficacy. We show that region exhaustive patterns are better at detecting untargeted LPB faults compared to patterns obtained using gate exhaustive or traditional stuck-at fault models.
Keywords :
automatic test pattern generation; failure analysis; fault diagnosis; logic gates; logic testing; ATPG; device failure mechanisms; gate-exhaustive fault model; logic proximity bridge fault model; region-exhaustive fault model; single stuck-at faults comparison; Automatic test pattern generation; Bridge circuits; Circuit faults; Circuit testing; Failure analysis; Fault detection; Geometry; Geophysical measurement techniques; Ground penetrating radar; Logic testing;
Conference_Titel :
Asian Test Symposium, 2007. ATS '07. 16th
Conference_Location :
Beijing
Print_ISBN :
978-0-7695-2890-8
DOI :
10.1109/ATS.2007.78