False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults

While design-for-testability (DFT) techniques are generally used in order to reduce test generation complexity, they induce over-testing problems. In general, DFT techniques make a large number of untestable paths testable. However delay on the path that becomes testable does not affect circuit performance because the path was originally untestable. Therefore we consider testing such path to be over-testing. In this work, we reduce the over-testing by identifying false paths using register transfer level information. Our method identifies a subset of false paths within a reasonable time. Experimental results for some RTL benchmark circuits show the effectiveness of our false path identification method.