A RTL Testability Analyzer Based on Logical Virtual Prototyping

In this paper, we propose a novel RTL testability analyzer based on logical virtual prototyping. A very fast synthesis engine is utilized to create a gate level hierarchical netlist with generic gates, which we call a logical virtual prototype, in this paper. Subsequently, ATPG and testability analysis are performed on the logical virtual prototype to provide RTL designers with a wealth of information that would allow them: (1) Accurately estimate / predict test coverage. (2) Generate patterns that can be used for gate-level design. (3) Identify hard-to-test design blocks in RTL, which can then be redesigned to improve coverage.