DocumentCode :
2197565
Title :
Optimized Assignment Coverage Computation in Formal Verification of Digital Systems
Author :
Nabi, M. ; Shojaei, H. ; Mohammadi, Soheil ; Navabi, Zainalabedin
Author_Institution :
Tehran Univ., Tehran
fYear :
2007
fDate :
8-11 Oct. 2007
Firstpage :
172
Lastpage :
177
Abstract :
Model checking thoroughly verifies the design correctness with respect to a specification. When the verification process succeeds, we can only postulate the correctness of the design relative to the given specification. How far can we affirm the verified design implements all the behavior of the desired system? With this regard we need to estimate the completeness of the properties by using some coverage metrics. In this paper, we have proposed a new metric called assignment coverage and an optimized method to overcome the intensive computations required for the multiple transformations among the abstract layers in the verification tool. The proposed coverage computation method provides adequate information to complete the set of properties. Finally, we have applied the proposed metric to some verification benchmark to reveal the effectiveness of this metric in finding undetected coverage holes.
Keywords :
formal verification; hardware description languages; high level synthesis; abstract layer; design correctness; digital system formal verification; model checking; optimized assignment coverage computation; Computational modeling; Condition monitoring; Counting circuits; Design automation; Design optimization; Digital systems; Formal verification; Genetic mutations; Optimization methods; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asian Test Symposium, 2007. ATS '07. 16th
Conference_Location :
Beijing
ISSN :
1081-7735
Print_ISBN :
978-0-7695-2890-8
Type :
conf
DOI :
10.1109/ATS.2007.40
Filename :
4388005
Link To Document :
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