Scalable and configurable software/hardware development for voice over packet networks

This paper investigates the use of a scalable and configurable architecture on a voice over packet (VoP) network application consisting of an ensemble of signal processing components including a speech codec, and an echo canceller. Each of these components imposes different demands on processor resources and the processor engines can be configured to suit the needs of the application. This paper discusses system-on-chip (SoC) design methodology and the implementation of the VoP application and compares the performance of VoP components with various processor configurations.