Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits

This paper analyzes the logic errors in digital circuits due to the presence of simultaneous switching noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called ´minimum switch condition´ is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called ´signal coherence condition´ is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction. DFT and ATPG recommendations are derived from this analysis.