DocumentCode
2197943
Title
Simulating Open-Via Defects
Author
Spinner, Stefan ; Jiang, Jie ; Polian, Ilia ; Engelke, Piet ; Becker, Bernd
Author_Institution
Albert-Ludwigs-Univ., Freiburg
fYear
2007
fDate
8-11 Oct. 2007
Firstpage
265
Lastpage
270
Abstract
Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows efficient simulation on gate level. The simulator takes oscillation caused by open-via defects into account and quantifies its impact on defect coverage. The flow can be employed for manufacturing test as well as for defect diagnosis.
Keywords
CMOS integrated circuits; integrated circuit manufacture; nanoelectronics; IC manufacturing defects testing; electrical parameter extraction; nanoscale manufacturing processes; open-via defects; systematic failure mechanism; Circuit faults; Circuit simulation; Computational modeling; Computer simulation; Failure analysis; Fault detection; Integrated circuit interconnections; Manufacturing processes; Semiconductor device modeling; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2007. ATS '07. 16th
Conference_Location
Beijing
ISSN
1081-7735
Print_ISBN
978-0-7695-2890-8
Type
conf
DOI
10.1109/ATS.2007.72
Filename
4388023
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