Title :
Programmable Logic BIST for At-speed Test
Author :
Huang, Yu ; Lin, Xijiang
Author_Institution :
Mentor Graphics Corp., Marlborough
Abstract :
In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing faults in different intra/inter clock domains when the maximum number of applied BIST test patterns is specified. Experimental results show the effectiveness of the proposed method on achieving higher test coverage than the method with test patterns evenly distributed among different test sessions.
Keywords :
built-in self test; clocks; logic design; logic testing; programmable logic devices; at-speed test; build-in-self-test; intra/inter clock domains; multiple clock frequency; programmable logic BIST controller; static analysis method; Built-in self-test; Clocks; Frequency; Logic design; Logic testing; Optimization methods; Pattern analysis; Programmable control; Programmable logic arrays; Programmable logic devices;
Conference_Titel :
Asian Test Symposium, 2007. ATS '07. 16th
Conference_Location :
Beijing
Print_ISBN :
978-0-7695-2890-8
DOI :
10.1109/ATS.2007.83
