Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan

Author

Xu, Gefu ; Singh, Adit D.

Author_Institution

Auburn Univ., Auburn

fYear

2007

fDate

8-11 Oct. 2007

Firstpage

335

Lastpage

340

Abstract

Enhanced scan designs support high coverage TDF testing but with significant overhead. We present a flip-flop selection strategy for partial enhanced scan designs that offers a favorable trade-off between coverage and overhead. Experimental results using commercial ATPG tools show that 60-90% of the TDF coverage benefits of enhanced scan can be achieved at 10-30% of the cost.

Keywords

automatic test pattern generation; fault diagnosis; flip-flops; logic testing; ATPG tools; TDF coverage; TDF testing; automatic test pattern generation; flip-flop selection; partial enhanced scan; transition delay fault testing; Automatic test pattern generation; Circuit testing; Clocks; Delay; Flip-flops; Logic testing; Semiconductor device testing; Stress; Timing; USA Councils;

fLanguage

English

Publisher

ieee

Conference_Titel

Asian Test Symposium, 2007. ATS '07. 16th

Conference_Location

Beijing

ISSN

1081-7735

Print_ISBN

978-0-7695-2890-8

Type

conf

DOI

10.1109/ATS.2007.96

Filename

4388035

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2198210