Improving Test Pattern Compactness in SAT-based ATPG

Automatic test pattern generation (ATPG) is one of the core problems in testing of digital circuits. ATPG algorithms based on Boolean Satisfiability (SAT) turned out to be very powerful, due to recent advances in SAT- based proof engines. SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. But due to the SAT provers, a major drawback of the resulting test patterns is that a large number of input bits is specified. Thus, the resulting patterns are not well suited Automatic Test Pattern Generation (ATPG) is one of the core problems in testing of digital circuits. ATPG algorithms based on Boolean Satisfiability (SAT) turned out to be very powerful, due to recent advances in SAT- based proof engines. SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. But due to the SAT provers, a major drawback of the resulting test patterns is that a large number of input bits is specified. Thus, the resulting patterns are not well suited for test compaction and compression. In this paper we present techniques to increase the number of unspecified bits in test patterns generated by SAT-based ATPG tools. We make use of structural properties of the circuit and apply local don´t cares. Experimental results on industrial designs show significant reductions of up to 97% for test compaction and compression. In this paper we present techniques to increase the number of unspecified bits in test patterns generated by SAT-based ATPG tools. We make use of structural properties of the circuit and apply local don´t cares. Experimental results on industrial designs show significant reductions of up to 97%.