Discrete event simulation on a MIMD parallel computer: algorithm optimization or hardware acceleration?

Discrete event simulation is a widely used technique to analyze systems ranging from queueing models to digital electronic circuits. Except for very sample problems, this type of application is very demanding on computing resources. This problem has traditionally been addressed in two ways. A first software-based approach is aimed at optimizing the performance of the algorithm that implements the critical abstract data type (the event list) on a sequential computer. The second approach is the design of algorithms that are aimed at exploiting the opportunities offered by new (parallel) computer architectures. A comparison of both approaches is made, resulting in the identification of a parallel computer architecture that will significantly improve the performance of discrete event simulation codes. Each node in this architecture consists of a general-purpose processor (a transputer) and an application-specific circuit (ASIC). The specification of the VLSI implementation in Occam2 not only allows an easy verification of the architecture, but also allows one to tune the design so that the goals of high performance and a silicon-efficient implementation can be achieved at the same time