DocumentCode :
2198754
Title :
A Study of Power Trade-offs in Translation Lookaside Buffer Structures
Author :
Ballesil, Anastacia P. ; Alarilla, Luis M., Jr. ; Alarcon, Louis P.
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of the Philippines, Quezon City
fYear :
2006
fDate :
14-17 Nov. 2006
Firstpage :
1
Lastpage :
4
Abstract :
Power consumption is now becoming equally as important as performance in microprocessor systems. Two major sources of processor power consumption are its clock tree and memory hierarchy. One particular area that can be explored for possible power reduction is the translation lookaside buffer (TLB). TLBs are small caches used to speed up virtual-to-physical address translation. The aim of this study is to design and implement different TLB design structures using VHDL. The structures are laid-out using 0.25 mum CMOS standard cells and then analyzed and characterized in terms of area, performance and power consumption. Results show that compared to the different structures considered in this study, banked associative structures consume the least power and occupy the smallest silicon area, with a minimal effect on delay
Keywords :
CMOS memory circuits; buffer storage; hardware description languages; low-power electronics; microprocessor chips; 0.25 micron; CMOS standard cell; TLB; VHDL; hardware description languages; memory hierarchy; microprocessor system; power consumption; translation lookaside buffer; virtual-to-physical address translation; Associative memory; CADCAM; Computer aided manufacturing; Decoding; Energy consumption; Memory management; Microprocessors; Random access memory; Read-write memory; Virtual private networks;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2006. 2006 IEEE Region 10 Conference
Conference_Location :
Hong Kong
Print_ISBN :
1-4244-0548-3
Electronic_ISBN :
1-4244-0549-1
Type :
conf
DOI :
10.1109/TENCON.2006.343927
Filename :
4142159
Link To Document :
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