The layout implementations of high-speed low-power MCML cells

MOS Current-Mode Logic (MCML) is usually used for high-speed applications. In this paper, the design method of the low-power high-speed MOS MCML is addressed. The layout implementations of MCML basic gates are presented at a NCSU FreePDK 45 nm technology. The post-layout simulations are carried out. For normal supply voltage, the MCML basic gates can save more energy and have better performance than the traditional CMOS counterparts at 1GHz or higher operation frequencies. Scaling down the supply voltage of MCML circuits is investigated. The results show that the power consumption of MCML circuits can be reduced by lowering the supply voltage with a little performance degrading.