DocumentCode
2199021
Title
Design of Deblocking Filter in H.264/AVC
Author
Huang Yan ; He Jing
Author_Institution
Inf. Eng. Sch., Commun. Univ. of China, Beijing, China
fYear
2009
fDate
20-22 Sept. 2009
Firstpage
1
Lastpage
3
Abstract
The design methodology of the deblocking filter in H.264/AVC is presented in this paper. To improve the filtering performance, an improved parallel filtering order is proposed. The deblocking filter is implemented with a fully pipelined datapath and the vertical edge and horizontal edge can be filtered simultaneously. And it takes 116 clock cycles to perform a 4:2:0 macroblock filtering. The design is implemented and verified on FPGA.
Keywords
edge detection; field programmable gate arrays; filtering theory; pipeline processing; video coding; FPGA; H.264/AVC; deblocking filter design; fully pipelined datapath; horizontal edge filtering; macroblock filtering; parallel filtering order; vertical edge filtering; Adaptive filters; Automatic voltage control; Clocks; Computer architecture; Field programmable gate arrays; Information filtering; Information filters; Random access memory; Read-write memory; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Management and Service Science, 2009. MASS '09. International Conference on
Conference_Location
Wuhan
Print_ISBN
978-1-4244-4638-4
Electronic_ISBN
978-1-4244-4639-1
Type
conf
DOI
10.1109/ICMSS.2009.5305713
Filename
5305713
Link To Document