Title :
A high-speed serial data acquisition scheme based on Nios II
Author :
Zhang, Wei ; Shen, Jun
Author_Institution :
Beijing Inst. of Technol., Beijing, China
Abstract :
This paper proposes a high speed serial data acquisition scheme.The scheme adopts Nios II soft processor in FPGA instead of application of specific chips in digital system to realize and control serial data acquisition,and especially focuses on the hardware designment with Quartus II and software development with Nios II EDS.This design shortens the design processs,simplifles the circuits,and increases data reliability. Simulation and testing results show that the data receiving is accurate,which verifies the validity of the design.
Keywords :
data acquisition; field programmable gate arrays; network synthesis; software engineering; FPGA; Nios II soft processor; Quartus II; data reliability; design processs; high-speed serial data acquisition scheme; software development; Data acquisition; Field programmable gate arrays; Hardware; IP networks; Process control; Registers; Testing; FPGA; Nios II; serial data acquisition;
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Zhejiang
Print_ISBN :
978-1-4577-0320-1
DOI :
10.1109/ICECC.2011.6067869
