Functional Unit Selection in Superscalar Microprocessors for Low Power

A novel technique is introduced to reduce power consumption in functional units (FU). Extra slower FU with lower per-execution energy consumption are added into a processor. Thus, through code scheduling, instructions whose results are not immediately referenced after completion are issued to these power-frugal FU. Simulation suggests a prospect of saving 20% to 30% energy consumption in addition instructions while still improving the performance