A leakage reduction scheme for single phase energy-recovery memory using dual threshold CMOS

This paper presents a leakage reduction scheme for single phase energy-recovery memory using dual threshold CMOS. Dual Threshold Asymmetric Complementary Pass- Transistor Adiabatic Circuits (DTA-CPAL) are proposed to reduce their leakage power dissipations. A 32 × 32 energy- recovery memory is demonstrated using the proposed DTA-CPAL circuits. All circuits are verified using HSPICE with 45 nm and 90 nm CMOS process in a clock frequency range from 50 MHz to 200 MHx. BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are obviously reduced both in work mode and idle mode compared with the single threshold one.