Floating point computation in SIMD massively parallel computers

This paper focuses on the computational capabilities of the processing elements (PEs) in SIMD massively parallel computers and particularly addresses the problem of the acceleration of floating point computation. In this class of parallel computers, floating point operations are usually done either through standard floating point processors, such as in the Connection Machine CM-2, or through special hardware structures built in each PE, such as in MasPar MP-1. We consider a floating point design solution based on the utilization of two fast FIFOs in each PE. We introduce the model of a PE and give a measurement of the performances of the floating point routines with no additional hardware. Then we present our solution and show how it improves the performances. Finally, we discuss the results obtained and provide some concluding remarks