Addressing scheme for a parallel memory system

Describes the use of a fine grain parallel memory system using linear skewing schemes for storing multidimensional arrays of any size, and an addressing scheme based on the Chinese remainder theorem (CRT) that is compatible with the linear mapping. So, the number of memory banks and processing elements is fixed, whereas the size of the multidimensional arrays varies with the application of such a machine. We extend the well-known linear skewing scheme to multidimensional arrays which provide conflict-free access to all vectors of interest. We give the conditions over the range of the stored vector to enable a simple addressing scheme. The address generation is also discussed. To complete the parallel memory system, we present an interconnection network that is adapted to the mapping