Memory access reduction method for efficient implementation of vector-radix 2D fast cosine transform pruning on DSP

In this paper, we propose a novel memory access reduction method to minimize the memory accesses due to weighting factors (cosine coefficients in the computation diagram of vector-radix 2D FCT pruning) and input points for implementing vector-radix 2D FCT pruning on DSP processors. The proposed method reduces the number of memory accesses in two steps: 1) Reduce the number of weighting factors and 2) Combine butterflies at two stages in vector-radix 2D FCT pruning diagram to form an efficient butterfly structure in one stage and calculate them. The proposed method is applied to implement vector-radix 2D FCT pruning on TI TMSC320C64x DSP. Experimental results show that the proposed method can achieve average of 47.2% memory access reduction, average of 58.2% clock cycle reduction and average of 20% memory space saving for weighting factors to compute vector-radix 2D fast cosine transform pruning on DSP comparing with the conventional implementation.