Optimization design of reed-solomon decoder based on FPGA

Author

Tong, Liu ; Chuan, Zhang

Author_Institution

Coll. of Inf. & Commun. Eng., Harbin Eng. Univ., Harbin, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

368

Lastpage

371

Abstract

In order to improve anti-jamming capability, the tactical data link uses RS (31, 15) coding/decoding in data transmission. In this paper, a RS (31, 15) hardware decoder base on RIBM algorithm is introduced, and this decoder is designed and implemented by pipeline algorithm. To make up the key equation module´s deficient in the whole pipeline, a modified RIBM algorithm is proposed, and the logic resource is also reduced. Besides, the Chien search module and the Forney module are assembled and optimized, further simplifying the structure of the decoder.

Keywords

Reed-Solomon codes; circuit optimisation; decoding; field programmable gate arrays; logic design; military communication; pipeline processing; Chien search module; FPGA; Forney module; RIBM algorithm; RS (31, 15) hardware decoder; Reed-Solomon Decoder; antijamming capability; logic resource; optimization design; pipeline algorithm; Algorithm design and analysis; Clocks; Computer architecture; Decoding; Delay; Polynomials; FPGA; RIBM algorithm; RS code; data link; optimize;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Zhejiang

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6067928

Filename

6067928