Sorena: New on Chip Network Topology Featuring Efficient Mapping and Simple Deadlock Free Routing Algorithm

This paper presents a new topology for network-on-chip (NoC) called “Sorena”. The proposed topology is made by merging of 4-node basic models and then connecting edge nodes. Using a change in coordinate system of nodes, a simple, fast and deadlock-free routing algorithm has been suggested. Compared to 2D Mesh which is the most common topology in on chip networks with its high expandability and simple routing algorithms, Sorena shows better average latency and power consumption. Finally, Onyx mapping, one of the best algorithms at mapping of cores onto Mesh based NoC architectures, has been implemented onto Sorena. Results demonstrate that Sorena also has much more suitable structure to implement mapping algorithms comparing to Mesh topology.