DocumentCode
2200808
Title
Partial correctness of C-MOS switching circuits: an exercise in applied logic
Author
Hoare, C.A.R. ; Gordon, M.J.C.
Author_Institution
Comput. Lab., Oxford Univ., UK
fYear
1988
fDate
0-0 1988
Firstpage
28
Lastpage
36
Abstract
The possibility of extending some of the logical methods that have been recommended for the design of software to the design of hardware, in particular, of synchronous switching circuits implemented in CMOS, is explored. The objective is to design networks that are known by construction. Things that can go wrong with circuits designed in this way are examined. The application of the techniques is discussed.<>
Keywords
CMOS integrated circuits; circuit CAD; switching circuits; CMOS switching circuits; applied logic; design; partial correctness; software; synchronous switching circuits; Design engineering; Digital circuits; Error correction; Hardware; Laboratories; Logic circuits; Manufacturing; Mathematics; Software design; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Logic in Computer Science, 1988. LICS '88., Proceedings of the Third Annual Symposium on
Conference_Location
Edinburgh, UK
Print_ISBN
0-8186-0853-6
Type
conf
DOI
10.1109/LICS.1988.5098
Filename
5098
Link To Document