Software tool for efficient FPGA design of direct data domain approach for space-time adaptive processing

Space-time adaptive processing algorithms have been proven to be a very effective way to mitigate the effects of multipath and interference. Due to the fast-changing clutter scenario, the stationary property of the data is destroyed and fails if the interference scenario ever becomes heterogeneous. Direct data domain (D³) methods can accommodate non-stationary data and can effectively suppress the clutter. However, the computation of D³ is very intensive. It is desirable to implement the D³ algorithm on a FPGA architecture for real-time applications. FPGAs can accommodate parallel and pipelined architecture. Here, the first FPGA design for the D³ algorithm and a new software package are presented. The software tool is capable of auto-generating a fully optimised VHDL representation of D³ and provides various performance parameters. The tool can be used by the designer to develop an overall system on chip (SoC) by using various constraints and options to meet certain performance criteria. Experimental results demonstrate that the authors´ hardware version of the D³ algorithm can significantly outperform an equivalent software version.