An Efficient Implementation of Constrained Partitioned Processor for Broadband Antenna Array Without Steering Delays

A constrained partition processor is an implementation of a broadband time domain antenna array processor using a fixed main beam steered in the look direction and a set of auxiliary beams to remove unwanted directional noise from the main beam. The weights of the auxiliary beams are constrained to block the desired signal. This paper presents a scheme to estimate the weights of the auxiliary beams requiring much less computation time than existing techniques