A layout dependent and bias independent scalable substrate model for CMOS RF transistors

Author

Suravarapu, Ravikanth ; Mayaram, Kartieya ; Shi, C. J Richard

Author_Institution

Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA

fYear

2002

fDate

2002

Firstpage

217

Lastpage

220

Abstract

The dependence of the substrate resistance for MOS transistor RF modeling on biasing is studied from device simulations for a 0.5 μm CMOS process. Though the substrate resistance is found to be bias dependent, the error incurred by assuming a constant value equal to the DC resistance is not significant. A scalable model for the substrate resistance of multiple gate fingers is developed. This model is simple to extract and gives good agreement for the output admittance.

Keywords

MOSFET; electric admittance; electric resistance; semiconductor device models; substrates; CMOS RF transistors; DC resistance; bias independent substrate model; biasing; device simulations; layout dependent substrate model; multiple gate fingers; output admittance; scalable substrate model; substrate resistance; CMOS process; Electrical resistance measurement; Fingers; Frequency measurement; Immune system; Joining processes; MOSFETs; Phase measurement; Radio frequency; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio and Wireless Conference, 2002. RAWCON 2002. IEEE

Print_ISBN

0-7803-7458-4

Type

conf

DOI

10.1109/RAWCON.2002.1030156

Filename

1030156

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2202028