Title :
A single-loop second-order ΔΣ frequency discriminator
Author :
Bax, Walt T. ; Copeland, Miles A. ; Riley, Tom A D
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
A new single-loop architecture for a second-order ΔΣ frequency discriminator suitable for RF applications is presented. This architecture can be realized using mostly digital blocks and has several advantages over multi-loop structures which are susceptible to analog non-idealities. A 2 GHz version of the ΔΣ frequency discriminator targeted to wireless mobile applications has been implemented in a 0.8 μm BiCMOS process. Measured results show a peak signal-to-noise ratio of 45 dB in a 200 kHz bandwidth
Keywords :
BiCMOS integrated circuits; UHF integrated circuits; discriminators; land mobile radio; radio receivers; sigma-delta modulation; superheterodyne receivers; ΔΣ frequency discriminator; 0.8 micron; 2 GHz; 200 kHz; 45 dB; BiCMOS process; RF applications; UHF; second-order type; single-loop architecture; wireless mobile applications; Analytical models; BiCMOS integrated circuits; Consumer electronics; Digital modulation; Digital signal processing; Frequency conversion; Frequency estimation; Frequency synthesizers; PSNR; Phase locked loops; Phase modulation; Radio frequency; Receivers; Timing;
Conference_Titel :
Analog and Mixed IC Design, 1996., IEEE-CAS Region 8 Workshop on
Conference_Location :
Pavia
Print_ISBN :
0-7803-3625-9
DOI :
10.1109/AMICD.1996.569375
