Title :
Low-power high-speed ECL circuit with 0.5-μm rule and 30-GHz fT technology
Author :
Tahara, Akinori ; Hashimoto, Kenji ; Katakura, Hiroshi ; Amano, Isao ; Deguchi, Tatsuya ; Sudo, Satoshi
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
Optimized self-aligned transistors for low-power ECL (emitter-coupled-logic) circuit applications are discussed. The ECL circuit was fabricated using a 0.5-μm rule and a 28-GHz f T technology and evaluated in terms of the propagation delay time of ring oscillators and a 1/8 static divider. The analysis of the circuit, the process design, and the npn transistor structure are discussed. A 39-ps/1.6-mW ECL circuit and a 12.5-GHz 1/8 static divider were obtained
Keywords :
bipolar integrated circuits; counting circuits; emitter-coupled logic; frequency dividers; integrated circuit technology; integrated logic circuits; oscillators; 0.5 micron; 1.6 mW; 12.5 GHz; 28 to 30 GHz; 39 ps; emitter-coupled-logic; high-speed ECL circuit; low-power ECL; npn transistor structure; process design; propagation delay time; ring oscillators; self-aligned transistors; static divider; submicron; Analytical models; Cutoff frequency; Delay effects; Electrodes; Epitaxial layers; Integrated circuit interconnections; Parasitic capacitance; Propagation delay; Resistors; Switching circuits;
Conference_Titel :
Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989
Conference_Location :
Minneapolis, MN
DOI :
10.1109/BIPOL.1989.69484
