Title :
A model for a reconfigurable fine-grained optoelectronic processor
Author :
Butrym, A.M. ; Craft, N. ; Guise, D. ; Murdocca, M. ; Sauer, F.
Author_Institution :
Dept. of Comput. Sci., Rutgers Univ., New Brunswick, NJ, USA
Abstract :
A model for a dataflow based processor is described in which a program written in a high level language is mapped directly to hardware. The concept is to reconfigure the interconnection network among an array of processing elements (PEs) to match the natural form of a computation, as represented by a dataflow graph. Communication among PEs is handled optically using free-space interconnects. A group of vertical cavity surface emitting lasers (VCSELs) is dedicated to each output port of a PE, which corresponds to an arc in a dataflow graph. Outputs of the VCSELs are imaged through a reconfigurable optical permutation network that redirects beams to their destinations. This combination of optics and electronics may support fine-grained parallelism while balancing time spent in communication with time spent in computation
Keywords :
integrated optoelectronics; optoelectronic devices; parallel machines; parallel processing; parallel programming; reconfigurable architectures; VCSELs; dataflow based processor; dataflow graph; fine-grained parallel; free-space interconnects; high level language; interconnection network; natural form; output port; processing elements; reconfigurable fine-grained optoelectronic processor; reconfigurable optical permutation network; vertical cavity surface emitting lasers; Computer networks; Hardware; High level languages; LAN interconnection; Multiprocessor interconnection networks; Optical fiber networks; Optical interconnections; Stimulated emission; Surface emitting lasers; Vertical cavity surface emitting lasers;
Conference_Titel :
Massively Parallel Processing Using Optical Interconnections, 1994., Proceedings of the First International Workshop on
Conference_Location :
Cancun
Print_ISBN :
0-8186-5832-0
DOI :
10.1109/MPPOI.1994.336642
