A high speed encoder for recursive systematic convolutive codes

Improving the quality of service is an important target in modern multimedia applications. The main keywords defining the quality of service are the data rate and the data transmission reliability. Error correcting codes are generally employed to achieve the reliability of the data transmission. The present trend is to achieve high data rates on low-cost designs (such as FPGAs). Most of the time, parallel architectures are required to process error correcting codes with high data throughput. In this paper an effective parallel architecture is proposed for recursive convolutive systematic encoders. It is based on parallel and pipelining techniques and can be applied to non-recursive encoders. Data rates up to 693 Gbits/s can be achieved on FPGA implementations.