Title :
A high speed encoder for recursive systematic convolutive codes
Author :
M´Sir, A. ; Monteiro, F. ; Dandache, A. ; Lepley, B.
Author_Institution :
Metz Univ., France
Abstract :
Improving the quality of service is an important target in modern multimedia applications. The main keywords defining the quality of service are the data rate and the data transmission reliability. Error correcting codes are generally employed to achieve the reliability of the data transmission. The present trend is to achieve high data rates on low-cost designs (such as FPGAs). Most of the time, parallel architectures are required to process error correcting codes with high data throughput. In this paper an effective parallel architecture is proposed for recursive convolutive systematic encoders. It is based on parallel and pipelining techniques and can be applied to non-recursive encoders. Data rates up to 693 Gbits/s can be achieved on FPGA implementations.
Keywords :
convolutional codes; error correction codes; field programmable gate arrays; hardware description languages; parallel architectures; pipeline processing; telecommunication computing; turbo codes; 693 Gbit/s; FPGA implementations; VHDL models; critical path; error correcting codes; fast encoders; high data throughput; high speed encoder; intermediate state generation; low-cost designs; multimedia; parallel architecture; pipelining techniques; quality of service; recursive systematic convolutive codes; turbo-code encoder; Cyclic redundancy check; Data communication; Error correction codes; Field programmable gate arrays; Multimedia systems; Parallel architectures; Pipeline processing; Quality of service; Throughput; Turbo codes;
Conference_Titel :
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
Print_ISBN :
0-7695-1641-6
DOI :
10.1109/OLT.2002.1030183
