Title :
A hierarchical architecture for concurrent soft error detection based on current sensing
Author :
Tsiatouhas, Y. ; Arapoyanni, A. ; Nikolos, D. ; Haniotakis, Th
Author_Institution :
Adv. Silicon Solutions Div., ISD S.A., Halandri, Greece
Abstract :
Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an important role towards this direction. In this paper we propose a hierarchical architecture for concurrent soft error detection. This architecture is based on current sensing techniques and provides very low area overhead, small detection times and negligible performance penalty on the functional circuit under check.
Keywords :
CMOS memory circuits; SPICE; SRAM chips; built-in self test; current comparators; current mirrors; error detection; fault diagnosis; fault tolerant computing; integrated circuit testing; radiation hardening (electronics); CMOS technology; SPICE simulation; combinational circuit; concurrent soft error detection; current mirrors; current sensing; hierarchical architecture; low area overhead; on-line testing; retry cycle; robust circuit design; sensing comparator; single event upsets; small detection times; soft error tolerance; time redundancy; transient faults; Circuit faults; Clocks; Costs; Crosstalk; Error analysis; Power supplies; Pulsed power supplies; Redundancy; Single event transient; Testing;
Conference_Titel :
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
Print_ISBN :
0-7695-1641-6
DOI :
10.1109/OLT.2002.1030184
