A statistical sampler for a new on-line analog test method

In this work a new strategy to the on-line test of analog circuits is presented. The technique presents a very low analog overhead and it is completely digital. For the System-on-Chip (SoC) environment, this allows the implementation of on-line test using processing power already present in the system. As all the signal processing is done in the digital domain, it allows use of a purely digital tester or a digital BIST technique. The main principle of operation is based on the observation of statistical properties of the circuit under test. Due to the low analog power and performance overhead, the proposed technique can be used to analyze the output of several stages of complex analog systems without the use of switches or analog multiplexors, as no additional AD converter is needed. This paper presents the fundamentals of the proposed test method and some preliminary results concerning linear analog systems.