Automatic test pattern generation for Iddq faults based upon symbolic simulation

Test generation for logic faults can also be used to enable Iddq sensing devices detect a large number of Iddq-testable faults such as stuck-on transistors and line bridging. However, there are some of these faults not covered by the stuck-at fault model that need particular attention. In this paper, we present a method to generate test patterns for short-circuit faults with difficult equivalence for the gate-level stuck-at model. A symbolic simulation of a circuit having been injected a set of faults is performed to obtain its functional response, which is given as a set of functions in terms of input and fault-selection Boolean variables. Such functions are operated to obtain a minimal set of appropriate test vectors, which can be directly used as part of the final test set, or fed into a gate-level ATPG to improve the switch-level fault coverage of its resulting test patterns.