Author :
Polian, Ilia ; Becker, Bernd
Author_Institution :
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
Abstract :
A BIST method enabling two-pattern testing at-speed without violating thermal constraints by introducing cool down periods is proposed. The application of the method is demonstrated based on a scalable BIST architecture. Applicability on IP cores is given since only a two-pattern test set is required as input.
Keywords :
automatic test pattern generation; built-in self test; cooling; integrated circuit testing; microprocessor chips; BIST method; IP cores; cool down periods; delay testing; heat dissipation; idle clock cycles; scalable architecture; stop & go BIST; two-pattern testing at-speed; Application software; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Delay; Energy consumption; Integrated circuit testing; Thermal force;
Conference_Titel :
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
Print_ISBN :
0-7695-1641-6
DOI :
10.1109/OLT.2002.1030198
