Title :
Some faults need an I/sub ddq/ test
Author :
Makar, Samy R. ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
Fault Simulation results of different implementations of 2-1 multiplexers and D-latches are presented. These results show that some faults can only be detected by I/sub ddq/ test. Simulation results also show that the "importance" of I/sub ddq/ as a test method can vary considerably with implementation.
Keywords :
CMOS logic circuits; electric current measurement; fault diagnosis; integrated circuit testing; leakage currents; logic testing; D-latches; I/sub ddq/ test; fault simulation; logic circuits; multiplexers; Circuit faults; Circuit simulation; Circuit testing; Current measurement; Delay; Electrical fault detection; Fault detection; Integrated circuit interconnections; Multiplexing; Voltage;
Conference_Titel :
IDDQ Testing, 1996., IEEE International Workshop on
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-8186-7655-8
DOI :
10.1109/IDDQ.1996.557841
