Adaptive IDDQ: how to set an IDDQ limit for any device under test

The combination of deep submicron technologies together with system on chip complexity has brought the device under test (DUT) quiescent supply current (IDDQ) into the milliamps range. This IDDQ level, modulated by electrical parameters and critical dimensions process spreads, makes almost impossible to detect the small current increase caused by the presence of a defect into the DUT. The integration of a limited size IDDQ cell into the DUT, combined with automatic test equipment measurements and calculations allows to define an IDDQ limit for every DUT during electrical wafer sort revitalizing a powerful way to prevent defective chips can reach the application field.