Automatic extraction of higher order interconnect parasitics for device level simulators for VHSIC applications

Author

Mokhtari, M. ; Juhola, T. ; Schuppener, G. ; Sellberg, F.

Author_Institution

Dept. of Electron., R. Inst. of Technol., Kista, Sweden

fYear

1996

fDate

13-14 Sep 1996

Firstpage

44

Lastpage

49

Abstract

The necessary routines for extraction of interconnect parasitics have been implemented in Cadence DFWII environment. The implementation allows choice of parasitics based on “pure-capacitive”, “RC-” or third order “LRC-” filter. Eye-diagram simulations on CMOS and bipolar gates on Si and HBT gates on InP, emulating MSI Very High Speed circuits, have shown that “LRC”-extraction of the power-lines in the case of CMOS in the GHz region is vital in predicting the circuit behaviour. The bipolar test-bed has shown considerably less sensitivity to power-lines. The signal path is more relevant for LRC-extraction in the latter

Keywords

circuit analysis computing; integrated circuit interconnections; integrated circuit modelling; very high speed integrated circuits; CMOS gate; Cadence DFWII; HBT gate; InP; LRC filter; MSI very high speed circuit; RC filter; Si; VHSIC; automatic extraction; bipolar gate; device level simulation; eye diagram; interconnect parasitics; power line; pure-capacitive filter; signal path; BiCMOS integrated circuits; CMOS technology; Degradation; Filters; Geometry; Indium phosphide; Integrated circuit interconnections; Integrated circuit modeling; Predictive models; Semiconductor device modeling; Solid modeling; Very high speed integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Analog and Mixed IC Design, 1996., IEEE-CAS Region 8 Workshop on

Conference_Location

Pavia

Print_ISBN

0-7803-3625-9

Type

conf

DOI

10.1109/AMICD.1996.569380

Filename

569380